set board_type kv260
set rtl_top_name rtl_top
set rtl_files {rtl_top.v cdc_fifo.v cdc_synchronizer.v dual_clk_ram.v shift_register.v shift_register_vector.v shift_register_factory.v vga_iface.v xlive_audio.v}
set pin_xdc_file {pins.xdc}
set timing_xdc_file {timings.xdc}
set project_name project_1
set project_dir project_1
set design_name design_1
set ps_ip xilinx.com:ip:zynq_ultra_ps_e
set ps_name zynq_ultra_ps_e_0
set init_rule xilinx.com:bd_rule:zynq_ultra_ps_e
set rtl_top_instance ${rtl_top_name}_0
if { $board_type eq "kr260" } {
set board_parts [get_board_parts "*:kr260_som:*" -latest_file_version]
set som_connection {som240_1_connector xilinx.com:kr260_carrier:som240_1_connector:1.0 som240_2_connector xilinx.com:kr260_carrier:som240_2_connector:1.0}
} else {
set board_parts [get_board_parts "*:kv260_som:*" -latest_file_version]
set som_connection {som240_1_connector xilinx.com:kv260_carrier:som240_1_connector:1.3}
}
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
always @(posedge clk)
begin
prev_vsync <= vsync;
end
// move white line
always @(posedge clk)
begin
if (reset == TRUE)
begin
count_line <= ZERO;
end
else
begin
if ((vsync == TRUE) && (prev_vsync == FALSE))
begin
if (count_line < 1279)
begin
count_line <= count_line + ONE;
end
else
begin
count_line <= ZERO;
end
end
end
end
// draw color bar
always @(posedge clkv)
begin
if (count_line_v == count_h)
begin // draw white line
color_r <= 255;
color_g <= 255;
color_b <= 255;
end
else if (count_h < 256)
begin
color_r <= count_h;
color_g <= ZERO;
color_b <= ZERO;
end
else if ((count_h > 511) && (count_h < 768))
begin
color_r <= ZERO;
color_g <= count_h - 512;
color_b <= ZERO;
end
else if (count_h > 1023)
begin
color_r <= ZERO;
color_g <= ZERO;
color_b <= count_h - 1024;
end
else
begin
color_r <= ZERO;
color_g <= ZERO;
color_b <= ZERO;
end
end
// audio test signal
reg signed [AUDIO_WIDTH-1:0] sample_l;
reg signed [AUDIO_WIDTH-1:0] sample_r;
wire [AUDIO_WIDTH*2-1:0] sample_data;
wire sample_full;
reg sample_en;
localparam DECL = (1 << AUDIO_WIDTH) * 440 / SAMPLE_FREQ;
localparam DECR = (1 << AUDIO_WIDTH) * 660 / SAMPLE_FREQ;
assign sample_data = {sample_l, sample_r};
always @(posedge clk)
begin
if (reseta == TRUE)
begin
sample_en <= FALSE;
sample_l <= ZERO;
sample_r <= ZERO;
end
else
begin
if (sample_full == FALSE)
begin
sample_en <= TRUE;
sample_l <= sample_l - DECL;
sample_r <= sample_r - DECR;
end
else
begin
sample_en <= FALSE;
end
end
end
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
always @(posedge clk_tx)
begin
if (reset_tx == TRUE)
begin
start <= FALSE;
busy <= FALSE;
end
else
begin
if (busy == FALSE)
begin
start <= TRUE;
busy <= TRUE;
end
else
begin
start <= FALSE;
if (completed == TRUE)
begin
busy <= FALSE;
end
end
end
end
always @(posedge clk_tx)
begin
if (reset_tx == TRUE)
begin
frame_counter <= 0;
end
else
begin
if (completed == TRUE)
begin
if (frame_counter == 383)
begin
frame_counter <= 0;
end
else
begin
frame_counter <= frame_counter + 1;
end
end
end
end
always @(posedge clk_tx)
begin
if ((start == TRUE) && (fc_odd == FALSE))
begin
audio_req <= TRUE;
end
else
begin
audio_req <= FALSE;
end
end
always @(posedge clk_tx)
begin
if (reset_tx == TRUE)
begin
audio_data0 <= ZERO;
end
else
begin
if (audio_valid == TRUE)
begin
audio_data0 <= audio_data;
end
end
end
always @(posedge clk_tx)
begin
if (fc_odd == FALSE)
begin
audio_data1 <= {cs_data, 2'b0, audio_data0[AUDIO_WIDTH*2-1:AUDIO_WIDTH], {(24-AUDIO_WIDTH){1'b0}}};
end
else
begin
audio_data1 <= {cs_data, 2'b0, audio_data0[AUDIO_WIDTH-1:0], {(24-AUDIO_WIDTH){1'b0}}};
end
end
always @(posedge clk_tx)
begin
if (fc_zero)
begin
preamble <= 4'b0001;
end
else
begin
if (fc_odd == FALSE)
begin
preamble <= 4'b0010;
end
else
begin
preamble <= 4'b0011;
end
end
end
always @(posedge clk_tx)
begin
if (start_d[6] == TRUE)
begin
data_tx <= {parity, audio_data1, preamble};
id_tx <= fc_odd;
end
end
always @(posedge clk_tx)
begin
if (reset_tx == TRUE)
begin
valid_tx <= FALSE;
end
else
begin
if (start_d[8] == TRUE)
begin
valid_tx <= TRUE;
end
else
begin
if (completed == TRUE)
begin
valid_tx <= FALSE;
end
end
end
end
always @(posedge clk_tx)
begin
parity <= ^audio_data1;
end
always @(posedge clk)
begin
if (addr[7:6] == 2'b00)
begin
data <= ram[addr];
end
else
begin
data <= 1'b0;
end
end
generate
initial
begin
if (AES_MODE == 1)
begin // AES mode
ram[8'h00] = 1'b1; // AES:1 S/PDIF:0
ram[8'h01] = 1'b0; // PCM:0 other:1
ram[8'h02] = 1'b1; // NO emphasis 100
ram[8'h03] = 1'b0;
ram[8'h04] = 1'b0;
ram[8'h05] = 1'b0; // Source sampling frequency locked:0 unlocked:1
// Sampling frequency auto:00 48k:01 44k:10 32k:11
if (SAMPLE_FREQ == 48000)
begin
ram[8'h06] = 1'b0;
ram[8'h07] = 1'b1;
end
else
begin
ram[8'h06] = 1'b1;
ram[8'h07] = 1'b0;
end
ram[8'h08] = 1'b0; // Stereophonic mode 0100
ram[8'h09] = 1'b1;
ram[8'h0a] = 1'b0;
ram[8'h0b] = 1'b0;
ram[8'h0c] = 1'b0; // 0000: No user information 0001:192bit user bits
ram[8'h0d] = 1'b0;
ram[8'h0e] = 1'b0;
ram[8'h0f] = 1'b0;
/*******************************************************************************
* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/ /**
*
* @file xdpdma_video_example.c
*
*
* This file contains a design example using the DPDMA driver (XDpDma)
* This example demonstrates the use of DPDMA for displaying a Graphics Overlay
*
* @note
*
* None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 aad 10/19/17 Initial Release
* 1.1 aad 02/22/18 Fixed the header
*</pre>
*
******************************************************************************/
/* 11/26/24 Modified by miya */
/***************************** Include Files *********************************/
/**************************** Type Definitions *******************************/
/*****************************************************************************/ /**
*
* Main function to call the DPDMA Video example.
*
* @param None
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None
*
******************************************************************************/
int main()
{
int Status;
Xil_DCacheDisable();
Xil_ICacheDisable();
xil_printf("DPDMA Generic Video Example Test \r\n");
Status = DpdmaVideoExample(&RunCfg);
if (Status != XST_SUCCESS) {
xil_printf("DPDMA Video Example Test Failed\r\n");
return XST_FAILURE;
}
xil_printf("Successfully ran DPDMA Video Example Test\r\n");
return XST_SUCCESS;
}
/*****************************************************************************/ /**
*
* The purpose of this function is to illustrate how to use the XDpDma device
* driver in Graphics overlay mode.
*
* @param RunCfgPtr is a pointer to the application configuration structure.
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*
*****************************************************************************/
int DpdmaVideoExample(Run_Config *RunCfgPtr)
/*****************************************************************************/ /**
*
* The purpose of this function is to initialize the application configuration.
*
* @param RunCfgPtr is a pointer to the application configuration structure.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void InitRunConfig(Run_Config *RunCfgPtr)
{ /* Initial configuration parameters. */
RunCfgPtr->DpPsuPtr = &DpPsu;
RunCfgPtr->IntrPtr = &Intr;
RunCfgPtr->AVBufPtr = &AVBuf;
RunCfgPtr->VideoMode = XVIDC_VM_1280x720_60_P;
RunCfgPtr->Bpc = XVIDC_BPC_8;
RunCfgPtr->ColorEncode = XDPPSU_CENC_RGB;
RunCfgPtr->UseMaxCfgCaps = 1;
RunCfgPtr->LaneCount = LANE_COUNT_2;
RunCfgPtr->LinkRate = LINK_RATE_270GBPS;
RunCfgPtr->EnSynchClkMode = 0;
RunCfgPtr->UseMaxLaneCount = 1;
RunCfgPtr->UseMaxLinkRate = 0;
}
/*****************************************************************************/ /**
*
* The purpose of this function is to initialize the DP Subsystem (XDpDma,
* XAVBuf, XDpPsu)
*
* @param RunCfgPtr is a pointer to the application configuration structure.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
int InitDpDmaSubsystem(Run_Config *RunCfgPtr)
{
u32 Status;
XDpPsu *DpPsuPtr = RunCfgPtr->DpPsuPtr;
XDpPsu_Config *DpPsuCfgPtr;
XAVBuf *AVBufPtr = RunCfgPtr->AVBufPtr;
/* Initialize the DisplayPort TX core. */
Status = XDpPsu_InitializeTx(DpPsuPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
} /* Set the format graphics frame for Video Pipeline*/
Status = XAVBuf_SetInputLiveVideoFormat(AVBufPtr, RGB_12BPC);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
} /* Set the output Video Format */
XAVBuf_SetOutputVideoFormat(AVBufPtr, RGB_8BPC);
/* Set the Audio Volume L, R, 0-255 */
XAVBuf_AudioMixerVolumeControl(AVBufPtr, 255, 255);
/* Configure Video pipeline for graphics channel */
XAVBuf_ConfigureGraphicsPipeline(AVBufPtr); /* Configure the output video pipeline */
XAVBuf_ConfigureOutputVideo(AVBufPtr); /* Disable the global alpha, since we are using the pixel based alpha */
XAVBuf_SetBlenderAlpha(AVBufPtr, 0, 0); /* Set the clock mode */
XDpPsu_CfgMsaEnSynchClkMode(DpPsuPtr, RunCfgPtr->EnSynchClkMode); /* Set the clock source depending on the use case.
* Here for simplicity we are using PS clock as the source*/
XAVBuf_SetAudioVideoClkSrc(AVBufPtr, XAVBUF_PS_CLK, XAVBUF_PS_CLK); /* Issue a soft reset after selecting the input clock sources */
XAVBuf_SoftReset(AVBufPtr);
XAVBuf_AudioSoftReset(AVBufPtr);
XAVBuf_SetAudioClock(SAMPLE_FREQ * 512);
return XST_SUCCESS;
}
/*****************************************************************************/ /**
*
* The purpose of this function is to setup call back functions for the DP
* controller interrupts.
*
* @param RunCfgPtr is a pointer to the application configuration structure.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void SetupInterrupts(Run_Config *RunCfgPtr)
{
XDpPsu *DpPsuPtr = RunCfgPtr->DpPsuPtr;
XScuGic *IntrPtr = RunCfgPtr->IntrPtr;
XScuGic_Config *IntrCfgPtr;
u32 IntrMask = XDPPSU_INTR_HPD_IRQ_MASK | XDPPSU_INTR_HPD_EVENT_MASK;